SEMATECH Reports New Approach to Simulate Transistor Noise
Tuesday, October 27, 2009 - 16:42
in Physics & Chemistry
Researchers from SEMATECH's Front End Processes (FEP) program have developed a comprehensive transistor noise model capable of extracting defect characteristics from low frequency noise data in advanced gate stack transistors using both conventional and novel dielectrics. The proposed model is a key step towards identifying and minimizing defects to support aggressive device scaling. SEMATECH`s results were presented at the IEEE Integrated Reliability Workshop (IRW) on Thursday, October 22, in Lake Tahoe, CA.