New simulation tool could shorten manufacturing design process

Novel research on improving the simulation performance of hardware models created in a language called SystemC, often used to shorten manufacturing design cycles to improve the time it takes to bring a product to the marketplace, has garnered a best paper award at the 15th Asia and South Pacific Design Automation Conference (ASP-DAC) for a team led by Sandeep Shukla, Virginia Tech associate professor of electrical and computer engineering (ECE), and three of his students.

Read the whole article on Physorg

More from Physorg